For ultra large scale integrated (ULSI) circuit application, the dimensions of devices are scaled down to sub-micron or deep sub-micron range. Self-aligned silicided (SALICIDE) process is the popular method to reduce the resistance of the gate, source and drain. Thus, CMOS devices with the self-aligned silicided process can increase the operation speed.
A so-called SAS (stacked amorphous silicon) method disclosed by Wu is proposed as a dopant diffusion source to form source and drain. An ultra-shallow source and drain junctions can be obtained by using the amorphous silicon layer as a diffusion source and by thermally driving the ions into the substrate. An article relating to the matter has been published by S. L. Wu, et al., in IEEE Trans. Electron Devices, Vol. ED-40, p. 1797, 1993. In this paper, a high performance shallow junction diode is formed by using an SAS (stacked amorphous silicon) as the dopant diffusion source.
Recently, A Hori et al. proposed devices with ultra-shallow source and drain junction by using 5 KeV ion implantation and rapid thermal annealing. This method can be used to suppress the short channel effect. In this article, the source and drain extensions are fabricated by ion implantation to obtain ultra-shallow profile. (A. Hori, et al., in IEDM Tech. Dig., p.485, 1994, entitled "A 0.05 .mu.m-CMOS with Ultra Shallow Source/Drain Junction Fabricated by 5 KeV Ion Implantation and Rapid Thermal Annealing".)
For ULSI circuits application, the thickness of the gate oxide is necessary to be scaled down to nanometer dimensions. Therefore, the reliability of the ultra thin oxide is a serious problem to the scaled devices. Typically, the reliability of the gate oxide is influenced by many factors, such as the hot carrier that is one of the major issues to degrade the performance of the devices such that even the supply voltage is reduced down to 2.5 V for 0.25 micron MOS. In order to provide reliable MOSFETs, many structures of the MOSFET have been proposed. For example, one of the prior art approaches to improve the hot carrier resistance is the use of a NICE (nitrogen implantation into CMOS gate electrode and source and drain) structure. The NICE structure is proposed by T. Kuroi, et al., in IEDM Tech. Dig., p. 325, 1993. In the structure, the surface channel PMOS with the p+ poly gate has been investigated in place of the buried channel with n+ poly gate. However, the high dose (higher than 4E15 atom/cm.sup.2) nitrogen implantation will cause a drastic increase in the sheet resistance of poly-Si gate, therefore the performance of the devices will be degraded by this matter. One relating article is "Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors with Lightly Doped Drain Structure", S. Shimizu, et al., Jpn. J. Appl. Phys., vol. 35, p. 802, 1996.
The hot carrier degration in LDD n-MOS is caused by the generation of interface states or electron traps in the sidewall spacers. For the NICE structure, the nitrided gate oxide under the gate electrode is not effective in suppressing the generation of interface state electron traps. Thus, S. Shimizu proposed a NISW (nitrogen implantation in the silicon oxide sidewall spacers) structure to solve the aforesaid issue. The issue can be suppressed due to the dangling bonds and weakened bonds formed at the interface between the sidewall spacers and the silicon substrate are occupied by the segregated nitrogen atoms.